library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is
port(a,b:in std_logic_vector(2 downto 0);y:out std_logic_vector(5 downto 0));
end entity mux;

architecture generator of mux is
component adder1 is 
	port (a,b,cin:in std_logic;sum,cout:out std_logic);
end component adder1;
component myand2 is
	port(ina,inb:in std_logic;aband:out std_logic);
end component myand2;
signal temp1:std_logic_vector(5 downto 0);
signal temp2:std_logic_vector(5 downto 0);
signal temp3:std_logic_vector(5 downto 0);
signal temp4:std_logic_vector(5 downto 0);
signal carry_out1:std_logic_vector(6 downto 0);
signal carry_out2:std_logic_vector(6 downto 0);

begin	
gen1:for i in 0 to 2 generate
	u1:myand2 port map(a(i),b(0),temp1(i));
	u2:myand2 port map(a(i),b(1),temp2(i+1));
	u3:myand2 port map(a(i),b(2),temp3(i+2));
end generate gen1;

gen2:for i in 0 to 5 generate
	u4:adder1 port map(temp1(i),temp2(i),carry_out1(i),temp4(i),carry_out1(i+1));
end generate gen2;
gen3:for i in 0 to 5 generate
	u5:adder1 port map(temp4(i),temp3(i),carry_out2(i),y(i),carry_out2(i+1));
end generate gen3;
end architecture generator;